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| MP4212 TOSHIBA Power MOS FET Module Silicon N&P Channel MOS Type (Four L2--MOSV in One) MP4212 High Power High Speed Switching Applications H-Switch Driver * * * * * * * 4-V gate drivability Small package by full molding (SIP 10 pin) High drain power dissipation (4-device operation) : PT = 4 W (Ta = 25C) Low drain-source ON resistance: RDS (ON) = 120 m (typ.) (N-ch) 160 m (typ.) (P-ch) High forward transfer admittance: |Yfs| = 5.0 S (typ.) (Nch) 4.0 S (typ.) (Pch) Low leakage current: IGSS = 10 A (max) (VGS = 16 V) IDSS = 100 A (max) (VDS = 60 V) Enhancement-mode: Vth = 0.8 to 2.0 V (VDS = 10 V, ID = 1 mA) Industrial Applications Unit: mm Absolute Maximum Ratings (Ta = 25C) Characteristics Drain-source voltage Drain-gate voltage (RGS = 20 k) Gate-source voltage Drain current DC Pulse Symbol VDSS VDGR VGSS ID IDP PD PDT EAS IAR EAR EART Tch Tstg 129 5 0.2 mJ 0.4 150 -55 to 150 C C Rating Nch 60 60 20 5 20 2.0 4.0 273 -5 Pch -60 -60 20 -5 -20 Unit V V V A W W mJ A JEDEC JEITA TOSHIBA 2-25A1C Weight: 2.1 g (typ.) Drain power dissipation (1-device operation, Ta = 25C) Drain power dissipation (4-device operation, Ta = 25C) Single pulse avalanche energy (Note 1) Avalanche current 1-device operation Repetitive avalanche energy (Note 2) 4-device operation Channel temperature Storage temperature range Note 1: Condition fo avalanche energy (single pulse) measurement Nch: VDD = 25 V, starting Tch = 25C, L = 7 mH, RG = 25 , IAR = 5 A Pch: VDD = -25 V, starting Tch = 25C, L = 14.84 mH, RG = 25 , IAR = -5 A Note 2: Repetitive rating; pulse width limited by maximum channel temperature Note 3: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook ("Handling Precautions"/Derating Concept and Methods) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). This transistor is an electrostatic-sensitive device. Please handle with caution. 1 2006-10-27 MP4212 Array Configuration 10 6 8 7 3 9 5 2 1 4 Thermal Characteristics Characteristics Thermal resistance from channel to ambient (4-device operation, Ta = 25C) Maximum lead temperature for soldering purposes (3.2 mm from case for t = 10 s) TL 260 C Symbol Max Unit Rth (ch-a) 31.2 C/W Electrical Characteristics (Ta = 25C) (Nch MOS FET) Characteristics Gate leakage current Drain cut-off current Drain-source breakdown voltage Gate threshold voltage Drain-source ON resistance Forward transfer admittance Input capacitance Reverse transfer capacitance Output capacitance Rise time Symbol IGSS IDSS V (BR) DSS Vth RDS (ON) |Yfs| Ciss Crss Coss tr VGS Turn-on time Switching time Fall time tf ton 10 V 0V 50 VDS = 10 V, VGS = 0 V, f = 1 MHz Test Condition VGS = 16 V, VDS = 0 V VDS = 60 V, VGS = 0 V ID = 10 mA, VGS = 0 V VDS = 10 V, ID = 1 mA VGS = 4 V, ID = 2.5 A VGS = 10 V, ID = 2.5 A VDS = 10 V, ID = 2.5 A Min 60 0.8 3.0 VOUT 25 ns 55 Typ. 0.21 0.12 5.0 370 60 180 18 Max 10 100 2.0 0.32 0.16 Unit A A V V S pF pF pF ID = 2.5 A RL = 12 VDD 30 V VIN: tr, tf < 5 ns, duty 1%, tw = 10 s 170 Turn-off time Total gate charge (Gate-source plus gate-drain) Gate-source charge Gate-drain ("miller") charge toff Qg Qgs Qgd VDD 48 V, VGS = 10 V, ID = 5 A 12 8 4 nC nC nC 2 2006-10-27 MP4212 Source-Drain Diode Ratings and Characteristics (Ta = 25C) Characteristics Continuous drain reverse current Pulse drain reverse current Diode forward voltage Reverse recovery time Reverse recovery charge Symbol IDR IDRP VDSF trr Qrr Test Condition IDR = 5 A, VGS = 0 V IDR = 5 A, VGS = 0 V dIDR/dt = 50 A/s Min Typ. 70 0.1 Max 5 20 -1.7 Unit A A V ns C Electrical Characteristics (Ta = 25C) (Pch MOS FET) Characteristics Gate leakage current Drain cut-off current Drain-source breakdown voltage Gate threshold voltage Drain-source ON resistance Forward transfer admittance Input capacitance Reverse transfer capacitance Output capacitance Rise time Symbol IGSS IDSS V (BR) DSS Vth RDS (ON) |Yfs| Ciss Crss Coss tr 0V VGS -10 V 4.7 VDS = -10 V, VGS = 0 V, f = 1 MHz Test Condition VGS = 16 V, VDS = 0 V VDS = -60 V, VGS = 0 V ID = -10 mA, VGS = 0 V VDS = -10 V, ID = -1 mA VGS = -4 V, ID = -2.5 A VGS = -10 V, ID = -2.5 A VDS = -10 V, ID =-2.5 A Min -60 -0.8 2.0 ID = -2.5 A RL = 12 VOUT 45 ns 55 Typ. 0.24 0.16 4.0 630 95 290 25 Max 10 -100 -2.0 0.28 0.19 Unit A A V V S pF pF pF Turn-on time Switching time Fall time ton tf VDD -30 V Turn-off time Total gate charge (gate-source plus gate-drain) Gate-source charge Gate-drain ("miller") charge toff VIN: tr, tf < 5 ns, duty 1%, tw = 10 s 200 Qg Qgs Qgd VDD -48 V, VGS = -10 V, ID = -5 A 22 16 6 nC nC nC Source-Drain Diode Ratings and Characteristics (Ta = 25C) Characteristics Continuous drain reverse current Pulse drain reverse current Diode forward voltage Reverse recovery time Reverse recovery charge Symbol IDR IDRP VDSF trr Qrr Test Condition IDR = -5 A, VGS = 0 V IDR = -5 A, VGS = 0 V dIDR/dt = 50 A/s Min Typ. 80 0.1 Max -5 -20 1.7 Unit A A V ns C 3 2006-10-27 MP4212 Marking MP4212 JAPAN Part No. (or abbreviation code) Lot No. A line indicates lead (Pb)-free package or lead (Pb)-free finish. 4 2006-10-27 MP4212 Nch MOS FET ID - VDS 5 10 8 6 4 3.5 20 10 16 8 6 Common source Tc = 25C ID - VDS 4 Drain current ID (A) 3 3 2 Common source Tc = 25C 1 VGS = 2.5 V 0 0 Drain current ID (A) 3.3 12 4.5 8 4 3.5 4 3 VGS = 2.5 V 0 0 0.4 0.8 1.2 1.6 2.0 4 8 12 16 20 Drain-source voltage VDS (V) Drain-source voltage VDS (V) ID - VGS 10 Common source 8 VDS = 10 V 2.0 VDS - VGS Common source VDS (V) Tc = 25C 1.6 Drain current ID (A) Drain-source voltage 6 1.2 8 0.8 5 0.4 ID = 2.5 A 4 2 25 Tc = -55C 100 0 0 2 4 6 8 10 0 0 4 8 12 16 20 Gate-source voltage VGS (V) Gate-source voltage VGS (V) |Yfs| - ID |Yfs| (S) 20 Common source 10 VDS = 10 V 0.5 RDS (ON) - ID Forward transfer admittance Drain-source ON resistance RDS (ON) () 0.3 VGS = 4 V 10 0.1 5 3 Tc = -55C 25 100 1 0.05 Common source Tc = 25C 0.5 0.3 0.5 1 3 5 10 30 0.03 0.3 0.5 1 3 5 10 Drain current ID (A) Drain current ID (A) 5 2006-10-27 MP4212 Nch MOS FET RDS (ON) - Tc () 0.4 Common source 20 10 5 3 10 3 IDR - VDS Drain-source ON resistance RDS (ON) 2.5 ID = 4 A 0.2 VGS = 4 V 4 2.5, 1.3 0.1 VGS = 10 V 1.3 Drain reverse current IDR 0.3 (A) 1 0.5 0.3 Common source Tc = 25C 0.1 0 1 VGS = 0, -1 V 0 -80 -40 0 40 80 120 160 -0.4 -0.8 -1.2 -1.6 -2.0 -2.4 Case temperature Tc (C) Drain-source voltage VDS (V) Capacitance - VDS 3000 2.5 Vth - Tc Common source 1000 Vth (V) (pF) 2.0 VDS = 10 V ID = 1 mA 500 300 Ciss Capacitance C Gate threshold voltage 100 1.5 100 50 Common source 30 VGS = 0 V f = 1 MHz Tc = 25C 10 0.3 0.5 0.1 Coss 1.0 Crss 0.5 1 3 5 10 30 50 Drain-source voltage VDS (V) 0 -80 -40 0 40 80 120 160 Case temperature Tc (C) Dynamic Input/Output Characteristics 80 Common source ID = 5 mA Tc = 25C 60 24 VDS 40 VDD = 48 V VDD = 48 V 8 16 VDS (V) 12 Drain-source voltage 24 20 12 VGS 4 0 0 20 40 60 0 80 Total gate charge Qg (nC) Gate-source voltage VGS (V) 12 6 2006-10-27 MP4212 Pch MOS FET ID - VDS -5 Common source Tc = 25C -4 -10 -3 -3 -2 -6 -8 -4 -3.5 -10 -10 -8 -8 -6 -4 Common source Tc = 25C ID - VDS Drain current ID (A) Drain current ID (A) -6 -3.5 -4 -3 -2 -2.5 VGS = -2 V -1 -2.5 VGS = -2 V 0 0 -0.4 -0.8 -1.2 -1.6 -2.0 0 0 -2 -4 -6 -8 -10 Drain-source voltage VDS (V) Drain-source voltage VDS (V) ID - VGS -10 Tc = -55C -8 25 100 Common source VDS = -10 V -2.0 VDS - VGS Common source VDS (V) Tc = 25C -1.6 Drain current ID (A) Drain-source voltage -6 -1.2 -4 -0.8 ID = -5 A -4 -3 -2 -0.4 -2 -1 0 0 ) 0 0 -2 -4 -6 -8 -10 -4 -8 -12 -16 -20 Gate-source voltage VGS (V) Gate-source voltage VGS (V) |Yfs| - ID |Yfs| (S) 30 Common source 10 5 3 100 1 0.5 0.3 -0.1 -0.3 -0.5 -1 -3 -5 -10 -30 VDS = -10 V 3 Common source Tc = 25C 1 0.5 0.3 RDS (ON) - ID Forward transfer admittance Tc = -55C 25 Drain-source ON resistance RDS (ON) () VGS = -4 V -10 0.1 0.05 0.03 -0.1 -0.3 -0.5 -1 -3 -5 -10 -30 Drain current ID (A) Drain current ID (A) 7 2006-10-27 MP4212 Pch MOS FET RDS (ON) - Tc () 1.0 Common source -30 Common source IDR - VDS Drain-source ON resistance RDS (ON) (A) 0.8 -10 -5 -3 Tc = 25C 0.6 ID = -5 A -2.5 VGS = -4 V -1.2 ID = -5, -2.5, -1.2 A VGS = -10 V 0 -80 -40 0 40 80 120 160 Drain reverse current IDR -10 -3 0.4 -1 -0.5 -0.3 0.2 -1 VGS = 0, 1 V -0.1 0 0.4 0.8 1.2 1.6 2.0 Case temperature Tc (C) Drain-source voltage VDS (V) Capacitance - VDS 5000 3000 -2.0 Vth - Tc Vth (V) Gate threshold voltage (pF) -1.6 1000 500 300 Common source 100 50 VGS = 0 V f = 1 MHz Crss Coss Ciss Capacitance C -1.2 -0.8 Tc = 25C 30 -0.1 -0.3 -0.4 Common source VDS = -10 V ID = -1 mA -1 -3 -10 -30 -100 Drain-source voltage VDS (V) 0 -80 -40 0 40 80 120 160 Case temperature Tc (C) Dynamic Input/Output Characteristics -50 Common source ID = -5 A Tc = 25C VDS -30 -12 VDD = -48 V -24 -12 -20 VDS (V) -40 -16 Drain-source voltage -20 -8 -10 VGS -4 0 0 8 16 24 32 0 40 Total gate charge Qg (nC) Gate-source voltage VGS (V) 8 2006-10-27 MP4212 PDT - Ta 8 (1) 1-device operation (2) 2-device operation (3) 3-device operation (4) 4-device operation Attached on a circuit board 160 Tch - PDT Tch (C) (W) (1) 120 (2) (3) (4) PDT 6 4 (4) (3) (2) Circuit board Channel temperature increase Total power dissipation 80 Circuit board Attached on a circuit board 40 (1) 1-device operation (2) 2-device operation (3) 3-device operation (4) 4-device operation 1 2 3 4 5 2 (1) 0 0 40 80 120 160 200 0 0 Ambient temperature Ta (C) Total power dissipation PDT (W) rth - tw 300 Curves should be applied in thermal limited area. (Single nonrepetitive pulse) The figure shows thermal resistance per device versus pulse width. (1) (4) Transient thermal resistance rth (C/W) 100 30 (3) (2) 10 Nch MOS FET 3 1 Pch MOS FET -No heat sink/Attached on a circuit board(1) 1-device operation (2) 2-device operation (3) 3-device operation Circuit board (4) 4-device operation 0.01 0.1 1 10 100 1000 0.3 0.1 0.001 Pulse width tw (s) 9 2006-10-27 MP4212 Safe Operating Area (be applicable to Nch MOS FET) 30 IDP max 100 s* ID max 3 100 ms* 1 10 ms* -30 Safe Operating Area (be applicable to Pch MOS FET) IDP max 100 s* -10 1 ms* ID max -3 100 ms* -1 10 ms* 10 Drain current ID (A) 1 ms* 0.3 *: Single nonrepetitive pulse Tc = 25C Curves must be derated linearly with increase in temperature. 0.1 1 3 10 30 Drain current ID (A) 300 100 -0.3 *: Single nonrepetitive pulse Tc = 25C Curves must be derated linearly with increase in temperature. -0.1 -1 -3 -10 -30 -100 -300 Drain-source voltage VDS (V) Drain-source voltage VDS (V) EAS - Tch (be applicable to Nch MOS FET) 200 500 EAS - Tch (be applicable to Pch MOS FET) Avalanche energy EAS (mJ) Avalanche energy EAS (mJ) 160 400 120 300 80 200 40 100 0 25 ) 0 25 50 75 100 125 150 50 75 100 125 150 Channel temperature Tch (C) Channel temperature Tch (C) 15 V -15 V BVDSS IAR VDD VDS 15 V -15 V BVDSS IAR VDD VDS TEST CIRCUIT Peak IAR = 5 A, RG = 25 VDD = 25 V, L = 7 mH TEST WAVE FORM 1 2 B VDSS AS = *L*I * B 2 - VDD VDSS TEST CIRCUIT Peak IAR = -5 A, RG = 25 VDD = -25 V, L = 14.84 mH TEST WAVE FORM 1 2 B VDSS AS = *L*I * B 2 - VDD VDSS 10 2006-10-27 MP4212 RESTRICTIONS ON PRODUCT USE * The information contained herein is subject to change without notice. 20070701-EN * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.).These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in his document shall be made at the customer's own risk. * The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. * Please contact your sales representative for product-by-product details in this document regarding RoHS compatibility. Please use these products in this document in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations. 11 2006-10-27 |
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